A Novel Implementation of Digital Circuits Using Mvl Function

The design of Multiple Valued Logic (MVL) digital circuits is performed by increasing the representation domain from the two level (N=2) switching algebra to N > 2 levels. Universal sets of MVL CMOS gates allow the synthesis and implementation of any MVL digital circuit. This paper proceed with: 1) the design and implementation of a universal set of IC gates, CMOS 0.25 um technology, that carry out extended AND operators: eANDl, eAND2, eAND3, Successor (SUC), and Maximum (MAX) operators to perform synthesis of any MVL digital circuits; and 2) the synthesis of an MVL multiplexer circuits based on the IC MVL gates. Implemented circuits demonstrate correct functionality of the implemented gates and feasibility of the MVL combinatorial circuit design.